Formal Semantics and Proof Techniques for Optimizing VHDL Models
Product ID: 146137331X
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Product Description
Formal Semantics and Proof Techniques for Optimizing VHDL Models
Technical Specifications
Country
USA
Brand
Springer
Manufacturer
Springer
Binding
Paperback
PartNumber
black & white illustrations
IsAdultProduct
Height
9.2499815
Length
6.0999878
Weight
0.59083886216
Width
0.42
ReleaseDate
2012-10-26T00:00:01Z
NumberOfItems
1
Author
Umamageswaran, Kothanda, Pandey, Sheetanshu L., Wilsey, Philip A.
